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| Features * * * * * * * * * * * * * * * * * Three DSPs and 24-bit Audio Router On-chip 32 kHz to 96 kHz Sampling Rate Enhanced P16 Processor with C Compiler New 48-bit Double-precision DSP Instructions Built-in 16K x 16 Flash Memory Built-in 8K x 24 RAM Secure Code - Copy Protected Direct Connection of LEDs, Switches Direct Connection of LCD Display 8 Channels for Audio In + Out DDR-SDRAM/SDRAM Support in Burst Mode MIDI In/Out 8-bit Parallel Interface Warm Start Power-down Deep Power-down (< 5 A) Using Built-in Power Switch LQFP80 Package Typical Applications: Effect Processing (reverb, echo, chorus, etc.), MP3 Decoding, Filtering, Sampling Rate Conversion, Professional Audio, Consumer Electronic, MP3 Player Audio Processing ATSAM3703 Highperformance Low-cost Effect Processor 1. Description The ATSAM3703 is a new member of the SAM3000 family of sound synthesis/processing ICs that uses the DSP array technology. It is designed for superior quality sound processing. The 16-bit processor has new instructions and a C compiler for quicker reliable firmware development. Total compatibility is maintained with the other members of the family. Applications written for the ATSAM3703 can be burned into the built-in Flash memory. This memory has specific features to avoid external read of the coded data, thus ensuring very effective copy protection. The minimum configuration for a product is ATSAM3703 + Codec. An external SDRAM/DDR-SDRAM is needed if the 8K internal RAM is not sufficient for extended delay line buffers, such as high-quality reverb. 6237A-DRMSD-29-May-06 2. DSP Array Block Diagram Figure 2-1. DSP Array Block Diagram DSP Array (3 P24 DSPs) External I/O to SDRAM or DDR SDRAM Embedded EEPROM 16K x 16 Embedded RAM 8K x 24 MMU Sync Bus Async Bus Enhanced 16-bit Processor (P16) I/Os, Timers, UARTs, Ports etc. Router Final ACC MIX Audio OUT Audio IN Audio I/0 Embedded ROM 1k x 16 BIOS and Debug External I/O 2 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 3. Functional Description 3.1 DSP Array The ATSAM3703 includes 3 on-chip DSPs. Each DSP (P24) is built around a 2K x 24 RAM and a 1K x 24 ROM. The RAM contains both data and P24 instructions; the ROM contains typical coefficients such as FFT cosines and windowing. A P24 sends and receives audio samples through the Sync Bus. It can request external data, such as compressed audio, through the Async Bus. Each P24 RAM can be accessed through the Async Bus. Each P24 is capable of typical MAC operation loops, including auto-indexing, bit reverse and butterfly (multiplication of complex numbers). It also includes specialized audio instructions such as state variable IIR filtering, envelope generation, linear interpolation and wavetable loop. The DSPs have new 48-bit double precision instructions for improved Pro Audio applications. One P24 is sufficient for processing one channel of MP3, implementing a multi-tap delay line or a multi-tap transversal filter. 3.2 Sync Bus The Sync Bus transfers data on a frame basis, typical frame rates being 32, 44.1, 48, 96 kHz. Each frame is divided into 64 time slots. Each slot is divided into 4 bus cycles. Each P24 is assigned a hardwired time slot (8 to 63), during which it may provide 24-bit data to the bus (up to 4 data samples). Each P24 can read data on the bus at any time, allowing inter P24 communication at the current sampling rate. Slots 0 to 7 are reserved for a specific router DSP, which also handles audio out, audio in, and remix send. 3.3 Async Bus The Async Bus is 24-bit data inside the chip and 16-bit outside. The P16 processor normally masters the Async Bus, it can read/write the P24 memories and the external or embedded ROM/RAM. However, each P24 can request a bus master cycle for accessing external ROM/RAM or other P24 memories. This allows efficient intercommunication between several P24s on asynchronous block basis. Specific P24 instructions FLOAT and FIX allow to convert fixed point DSP data to floating point 16 bits. This allows for 20-bit audio dynamic range when using 16-bit external memory. 3.4 Enhanced 16-bit Processor This is the new enhanced version of P16 processor with added instructions allowing optimized use of C compiler. Using the P16, widely used in Dream(R) products, maintains continuity for the large firmware investments from the SAM97xx series. A built-in ROM, connected to the P16 holds basic input/output software (BIOS) for peripherals such as UART, SmartMedia(R), MPU as well as a debugger which uses a dedicated asynchronous serial line. The firmware can reside on the built-in 16K x 16 EEPROM or it can be downloaded at power-up into the built-in 8K x 24 RAM from serial SmartMedia or host. 3.5 Memory Management Unit The MMU handles transfer requests between the external or embedded RAM/ROM, the P16 and the P24s through the Async Bus. The ATSAM3703 includes an on chip 8K x 24 RAM. 3 6237A-DRMSD-29-May-06 3.6 Router: Final ACC, MIX, Audio Out, Audio In This block includes a RAM, accessed through the Async Bus, which defines the routing from the Sync Bus to/from the Audio I/O or back to the Sync Bus (mix send). It takes care of mix and accumulation from Sync Bus samples. 8 channels of audio in and 8 channels of audio out are provided (4 stereo in/out, I2S format). The stereo audio in channels may have a different sampling rate than the audio out channels. In this case, one or more P24s take care of sampling rate conversion. 3.7 I/O The ATSAM3703 includes very versatile I/Os that share common pins for reduced pin count and small IC footprint. Most I/Os, when not used for a specific function, remain available as firmware controlled general-purpose pins. The following peripherals are included on chip: * 2 x 8-bit timers * 2 x 16-bit timers * Parallel slave 8-bit port, MPU401 compatible * Parallel master 8-bit port, for connection to SmartMedia and/or LCD display, switches, etc. * 2 x asynchronous bi-directional serial port (one used as debug interface) * Synchronous serial slave port (SPI type host connection) * Firmware controlled I/O pins 4 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 4. Typical Application Examples 4.1 Low Cost, High Quality Effect Figure 4-1. Switches, LCD Display MIDI ATSAM3703 ADC DAC Stereo Audio In/Out * High quality, full 24-bit multi-effects like reverb, chorus, compressor, etc. * Stereo 10-band graphic equalizer 4.2 Host-controlled MP3 Player Figure 4-2. Copmpressed Audio (from host) ATSAM3703 DAC Stereo Audio Out * ATSAM3703 firmware download from host (when using parallel interface) * Choice of host communication interfaces: - 8-bit parallel - Asynchronous serial - Synchronous serial (SPI * Full MP3 support including very low bit rates extension (ISO/IEC 13818-3). * Easily upgradable to other coding standards 4.3 Toys with "Artificial Intelligence" Figure 4-3. Switches, Motor Control ATSAM3703 ADC DAC Audio In/Out * Speech recognition * Learning functions * ADPCM record / play 5 6237A-DRMSD-29-May-06 5. DSP Capacity and I/O Configuration 5.1 DSP Considerations The ATSAM3703 include 3 x P24 DSPs. Table 5-1 lists the performance achievable by the P24. Table 5-1. Function MP3 decode Stereo reverb and chorus @48 kHz 31-band equalizer @96 kHz Stereo 31-band equalizer @48 kHz Performance with P24 P24s required 3 1 3 3 The ATSAM3703 runs firmware directly from an embedded EEPROM memory. It may also run firmware from local RAM. The ATSAM3703 is the ideal choice when external components count should be minimized and many I/O pins are required. 5.2 I/O Selection Considerations I/Os are organized in groups, which can be mutually exclusive because they share the same IC pins (refer to the pinout to identify the exclusions). The two main types of operation are host-controlled and stand-alone. 5.2.1 Host-controlled Operation There are 3 main ways to communicate with a host processor: * 8-bit parallel MPU type bi-directional interface signals: D7 - D0, CS, WR, RD, A0, IRQ * Asynchronous serial, MIDI_IN * Synchronous serial signals: SDIN, SCLK, SYNC, INT 5.2.2 Stand-alone Operation Possible stand-alone modes are: * Firmware into built-in EEPROM memory * Firmware into external SmartMedia. In this case, the firmware should reside in the SmartMedia reserved sectors starting at sector # 1. 6 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 6. Pinout 6.1 Pin Description Identical sharing number indicates multifunction pins. Pd indicates pin with built-in pull-down resistor. Pu indicates pin with built-in pull-up resistor. SSTL indicates a SSTL_2 class 1 compliant I/O pin. Table 6-1. Pin Name GND VC18 VC33 VC25 PWRIN PWROUT VREF D7 - D0 ATSAM3703 Pin Description Pin Number 1, 13, 24, 32, 40, 45, 49, 54, 61, 70 28, 46, 62, 77 4, 76 22, 33, 42, 50, 55 59 58 41 10, 9, 8, 7, 6, 5, 3, 2 Type PWR PWR PWR PWR PWR PWR In I/O Pd I/O Pd I/O Pd In Pd In Pd In In In In In Pu In Pu 1 Sharing Description Digital ground. All these pins should be returned to a ground plane Core power. All these pins should be returned to nominal 1.8V or to PWROUT if the built-in power switch is used. Periphery power. All these pins should be returned to nominal 3.3V. Memory PAD Power +2.25V to +3.6V. All VC25 pins should be returned to +2.5V (for DDR SDRAM) or 3.3V (for SDRAM) Power switch input, should be returned to nominal 1.8V even if the power switch is not used. Power switch output, should be connected to all VC18 pins if the power switch is used. VC25/2 reference for SSTL_2 pins. Slave 8-bit interface data. Output if CS and RD are low (read from chip), input if CS and WR are low (write to chip). Type of data defined by A0 input. SmartMedia data or other peripheral data General purpose I/O can individually be programmed as input or output Optional bit clocks and word selects for digital audio input. Used for sampling rate conversion, for external incoming digital audio such as AES/BEU or S/Pdif. Slave 8-bit interface address. Indicates data/status or data/ctrl transfer type (CS RD low or CS WR low) SmartMedia presence detect General purpose input pin Serial slave synchronous interface input clock Slave 8-bit interface chip select, active low. General purpose input pin I/O7 - I/O0 P0.7 - P0.0 CLAD3 - 0 WSAD3 - 0 A0 SMPD P0.10 SCLK CS P0.11 10, 9, 8, 7, 6, 5, 3, 2 10, 9, 8, 7, 6, 5, 3, 2 10, 9, 8, 7 6, 5, 3, 2 16 16 16 16 12 12 1 1 1 1 2 2 2 2 3 3 7 6237A-DRMSD-29-May-06 Table 6-1. Pin Name SYNC WR ATSAM3703 Pin Description (Continued) Pin Number 12 17 Type In Pu In Pu In Pu In Pu In Pu In Pu In Pu In Pu In Pu Out Out In I/O Out Out Out Out Out Out Out Out In Pd 7 7 8 8 9 9 Sharing 3 4 Description Serial slave synchronous interface input sync signal Slave 8-bit interface write, active low. D7-D0 data is sampled by chip on WR rising edge if CS is low SmartMedia configuration. This pin is sensed after power-up. If found low, it is assumed that a SmartMedia connector is present. The built-in firmware waits for SmartMedia SMPD. General purpose input pin Slave 8-bit interface read, active low. D7-D0 data is output when RD goes low and CS is low SmartMedia Ready Busy status General purpose input pin Serial MIDI in Serial slave synchronous interface input data Slave 8bit interface interrupt request. High when data is ready to be transferred from chip to host. Reset by a read from host (CS = 0 and RD = 0) SmartMedia read enable (RE), active low Freq sense, sensed at power up. Together with FS1, allows the firmware to know the operating freq of the chip (see FS1) General purpose I/O pin Serial slave synchronous interface data request, active low. Stereo channel 0 of digital audio output, I2S format Stereo channel 1 of digital audio output, I2S format General purpose output pin Stereo channel 2 of digital audio output, I2S format General purpose output pin Stereo channel 3 of digital audio output, I2S format Serial MIDI out Stereo audio data input, I2S format. Can operate on CLBD master rate or CLAD0 or CLAD01 external rate when sampling rate conversion is requested. DAAD0 has built-in pull-down. It may be left open if not used. Additional channel of stereo audio input, I2S format. Can operate on CLBD master rate or CLAD1 or CLAD01 external rate when sampling rate conversion is requested. DAAD1 has built-in pull-down. It may be left open if not used. SMC 17 4 P0.12 RD R|B P0.13 MIDI_IN SDIN 17 18 18 18 18 18 4 5 5 5 5 5 IRQ SMRE FS0 P0.8 INT DABD0 DABD1 P0.14 DABD2 P0.15 DABD3 MIDI_OUT 11 11 11 11 11 73 74 74 75 75 78 78 6 6 6 6 6 DAAD0 66 - DAAD1 67 In Pd - 8 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 Table 6-1. Pin Name ATSAM3703 Pin Description (Continued) Pin Number Type In Pd Sharing Description Additional channel of stereo audio input, I2S format. Can operate on CLBD master rate or CLAD2 external rate when sampling rate conversion is requested. DAAD2 has built-in pulldown. It may be left open if not used. Optional bit clock for digital audio inputs DAAD1-0. Used for sampling rate conversion, for external incoming digital audio such as AES/BEU or S/Pdif. Additional channel of stereo audio input, I2S format. Can operate on CLBD master rate or CLAD3 external rate when sampling rate conversion is requested. DAAD3 has built-in pulldown. It may be left open if not used. Optional word select for digital audio inputs DAAD1-0. Used for sampling rate conversion, for external incoming digital audio such as AES/BEU or S/Pdif. Freq sense, sensed at power up. FS1|FS0 allow firmware to know operating freq of chip as follows (optional):00- 6.9552 MHz 01- 9.6 MHz 10- 11.2896 MHz 11- 12.288 MHz General purpose Input pin Audio bit clock for DABD3-0. Audio bit clock for DAAD3-0 if the corresponding CLAD3-0 is not used. Audio left/right channel select for DABD3-0. Audio left/right channel for DAAD3-0 if the corresponding WSAD3-0 is not used. External DAC/Codec master clock. Same or double frequency as X2 pin. Can be programmed to be 128xFs, 192xFs, 256xFs, 384xFs, 512xFs, Fs being the DAC/Codec sampling rate. Multiplexed addresses for external SDRAM or DDR SDRAM memory General purpose I/O pins Clock Enable for external SDRAM or DDR SDRAM memory General purpose I/O pin Bank selects for external SDRAM or DDR SDRAM memory General purpose I/O pins External memory SDRAM or DDR SDRAM data bit 3 General purpose I/O pins DAAD2 68 10 CLAD01 68 In Pd 10 DAAD3 69 In Pd 11 WSAD01 69 In Pd In Pd In Pd Out 11 FS1 69 11 P0.9 CLBD 69 72 11 - WSBD 80 Out - CKOUT 71 35, 34, 31, 30, 29, 27, 26, 25, 23, 21, 20, 19 35, 34, 31, 30, 29, 27, 26, 25, 23, 21, 20, 19 57 57 37, 36 37, 36 52 52 Out Out SSTL I/O SSTL Out SSTL I/O SSTL Out SSTL I/O SSTL I/O SSTL I/O SSTL - WA11 - WA0 P2.11 - P2.0 WCKE P2.12 WBA1 - WBA0 P2.14 - P2.13 WDQ3 P1.3 12 12 13 13 14 14 15 15 9 6237A-DRMSD-29-May-06 Table 6-1. Pin Name SMCE WDQ2 P1.2 SMALE WDQ1 P1.1 SMWE WDQ0 P1.0 SMCLE WDQS P1.4 WCK P1.5 WCK P1.6 WRAS P1.7 WCAS P1.8 WWE P2.15 ATSAM3703 Pin Description (Continued) Pin Number 52 51 51 51 48 48 48 47 47 47 53 53 44 44 43 43 39 39 38 38 56 56 Type Out SSTL I/O SSTL I/O SSTL Out SSTL I/O SSTL I/O SSTL Out SSTL I/O SSTL I/O SSTL Out I/O SSTL I/O SSTL Out I/O Out I/O Out SSTL I/O Out SSTL I/O Out SSTL I/O SSTL Sharing 15 16 16 16 17 17 17 18 18 18 19 19 20 20 21 21 22 22 23 23 24 24 Description SmartMedia chip enable (CE), active low External memory SDRAM or DDR SDRAM data bit 2 General purpose I/O pin SmartMedia address latch enable (ALE) External memory SDRAM or DDR SDRAM data bit 1 General purpose I/O pin SmartMedia write enable (WE), active low External memory SDRAM or DDR SDRAM data bit 0 General purpose I/O pin SmartMedia command latch enable (CLE) Data Strobe for external DDR SDRAM memory General purpose I/O pin Positive clock for external SDRAM or DDR SDRAM memory General purpose I/O pin Negative clock for external DDR SDRAM memory General purpose I/O pin Row address strobe for external SDRAM or DDR SDRAM memory General purpose I/O pin Column address strobe for external SDRAM or DDR SDRAM memory General purpose I/O pin Write enable for external SDRAM or DDR SDRAM memory General purpose I/O pin 10 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 Table 6-1. Pin Name ATSAM3703 Pin Description (Continued) Pin Number Type Sharing Description External crystal connection. Standard frequencies are 6.9552 MHz, 9.6 MHz, 11.2896 MHz, 12.288 MHz. Max frequency is 12.5 MHz. An external clock (max. 1.8Vpp) can be connected to X1 using AC coupling (22pF). A built-in PLL multiplies the clock frequency by 4 for internal use. Master reset Schmitt trigger input, active low. RESET should be held low during at least 10ms after power is applied. On the rising edge of RESET, the chip enters an initialization routine, which may involve firmware download from an external SmartMedia, or host. Serial test input. This is a 57.6 kbauds asynchronous input used for firmware debugging. This pin is tested at power-up. The built-in debugger starts if STIN is found high. STIN has a built-in pull-down. It should be grounded or left open for normal operation. Serial test output. 57.6 kbauds async output used for firmware debugging. Power down input, active low. High level on this pin is typ. VC18. When PDWN is low, the oscillator and PLL are stopped, the power switch opens, and the chip enters a deep sleep mode (1A typ. consumption when power switch is used). To exit from power down, PDWN has to be set high then RESET applied. Alternate programmable power-downs are available which allow warm restart of the chip. Test input. Should be grounded or left open. X1 - X2 64, 63 - - RESET 14 In - STIN 65 In Pd - STOUT 79 Out - PDWN 60 In - TEST 15 In Pd - 11 6237A-DRMSD-29-May-06 6.2 Pinout by Pin Number ATSAM3703 Pinout by Pin Number Pin # 12 Name CS P0.11 SYNC Pin # 23 Name WA3 P2.3 Pin # 34 Name WA10 P2.10 Pin # 45 Name GND Table 6-2. Pin # 1 Name GND D0 I/O0 P0.0 WSAD0 D1 I/O1 P0.1 WSAD1 VC33 D2 I/O2 P0.2 WSAD2 D3 I/O3 P0.3 WSAD3 D4 I/O4 P0.4 CLAD0 D5 I/O5 P0.5 CLAD1 D6 I/O6 P0.6 CLAD2 D7 I/O7 P0.7 CLAD3 IRQ INT SMRE FS0 P0.8 2 13 GND 24 GND 35 WA11 P2.11 46 VC18 3 14 RESET 25 WA4 P2.4 36 WBA0 P2.13 47 WDQ0 SMCLE P1.0 WDQ1 SMWE P1.1 4 15 TEST A0 SMPD P0.10 SCLK WR SMC P0.12 RD R|B P0.13 MIDI_IN SDIN WA0 P2.0 26 WA5 P2.5 37 WBA1 P2.14 48 5 16 27 WA6 P2.6 38 WCAS P1.8 49 GND 6 17 28 VC18 39 WRAS P1.7 50 VC25 7 18 29 WA7 P2.7 40 GND 51 WDQ2 SMALE P1.2 8 19 30 WA8 P2.8 41 VREF 52 WDQ3 SMCE P1.3 9 20 WA1 P2.1 31 WA9 P2.9 42 VC25 53 WDQS P1.4 10 21 WA2 P2.2 32 GND 43 WCK P1.6 54 GND 11 22 VC25 33 VC25 44 WCK P1.5 55 VC25 12 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 Table 6-2. Pin # 56 57 58 ATSAM3703 Pinout by Pin Number (Continued) Pin # 61 62 63 Name GND VC18 X2 Pin # 66 67 68 Name DAAD0 DAAD1 DAAD2 CLAD01 DAAD3 WSAD01 FS1 P0.9 GND Pin # 71 72 73 Name CKOUT CLBD DABD0 Pin # 76 77 78 Name VC33 VC18 DABD3 MIDI_OUT Name WWE P2.15 WCKE P2.12 PWROUT 59 PWRIN 64 X1 69 74 DABD1 P0.14 DABD2 P0.15 79 STOUT 60 PDWN 65 STIN 70 75 80 WSBD 13 6237A-DRMSD-29-May-06 7. Mechanical Dimensions Figure 7-1. Thin 80-lead Quad Flat Pack (LQFP80) Table 7-1. Parameter A A1 A2 L D D1 E E1 P B LQFP Dimensions (mm) Min 0.05 1.35 0.45 Nominal 1.40 0.10 1.40 0.60 12.00 10.00 12.00 10.00 0.40 0.13 0.16 0.23 Max 1.60 0.15 1.45 0.75 14 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 8. Electrical Characteristics 8.1 Absolute Maximum Ratings *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature under bias.................................. -55 C to 125 C Storage Temperature ...................................... -65 C to 150 C Voltage on any pin X1, PWDN .................................................. -0.3 to VC18 + 0.3V Others ......................................................... -0.3 to VC33 + 0.3V Supply Voltage.......................................................................... VC18 ....................................................................-0.3V to 1.95V VC25 ......................................................................-0.3V to 3.6V VC33 ......................................................................-0.3V to 3.6V Maximum IOL per I/O pin................................................. 4 mA (except SSTL pins) Maximum IOH per I/O pin (except SSTL pins) .......................................................... 4 mA Maximum IOL per SSTL pin ............................................ 8 mA -VOUT = VTT - 0.405 Maximum IOH per I/O pin -VOUT = VTT + 0.405...................................................... 8 mA 8.2 Recommended Operating Conditions Recommended Operating Conditions Parameter Supply voltage Supply voltage (1) Table 8-1. Symbol VC18 VC33 PWRIN TA Note: Min 1.65 3 1.75 0 Typ 1.8 3.3 1.9 - Max 1.95 3.6 1.95 70 Unit V V V C Supply voltage PWRIN pin Operating ambient temperature 1. Operation at lower VC33 values down to VC18 is possible, however external timing may be impaired. Contact Atmel if you plan to use these circuits with VC33 outside the recommended operating range. 8.2.1 SSTL_2 Pads Memory pads of ATSAM3703 are SSTL_2 compliant. This feature allows direct interfacing with DDR SDRAM devices. 8.2.1.1 DDR SDRAM Operation When using DDR SDRAM memory, it is recommended to use the schematic in Figure 8-1 for Address, Data and Data Strobe. In power-down mode, the command lines (WRAS, WCAS, WWE, WCKE) have a fixed level, in contrast with address and data lines which are floating. To avoid consumption in power-down, RT can be not implemented on command lines. 15 6237A-DRMSD-29-May-06 Figure 8-1. Typical SSTL_2 Input/Output Environment Output Buffer VTT VC25 50 Ohm RT Receiver RS 25 Ohm VREF VOUT GND VIN Notes: 1. VC25 = 2.5V 2. VREF = 1.25 V 3. VTT = 1.25V (sink / source capability) Table 8-2. Symbol VC25 VREF RS RT Parameters Parameter Supply voltage Reference voltage Serial resistor Termination resistor Min 2.3 VC25/2 - 0.04 22.5 45 Typ 2.5 1.25 25 50 Max 2.75 VC25/2 + 0.04 27.5 55 Unit V V Ohm Ohm For more details on SSTL_2, refer to the EIA/JEDEC standard EIA/JESD8-9. 16 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 8.2.1.2 SDRAM OR GPIO OPERATION When using the SSTL_2 pad as SDRAM or GPIO signals, it is recommended to use the schematic in Figure 8-2. Figure 8-2. SSTL_2 in SDRAM or GPIO Operation Schematic Output Buffer VC25 Receiver VREF VOUT GND VIN Notes: 1. VC25 = 3.3V 2. VREF = 1.75V Table 8-3. Symbol VC25 VREF Parameters Parameter Supply voltage Reference voltage Min 3 VC25/2 - 0.04 Typ 3.3 1.75 Max 3.6 VC25/2 + 0.04 Unit V V 17 6237A-DRMSD-29-May-06 8.3 DC Characteristics DC Characteristics (TA= 25C, VC18 = 1.8V10%, VC33 = 3.3V10%, VC25 = 2.5V10% Parameter Low level input voltage, except X1, PDWN and SSTL pads High level input voltage, except X1, PDWN and SSTL pads Low level input voltage SSTL pads High level input voltage SSTL pads Low level input voltage X1, PDWN High level input voltage X1, PDWN Low level output voltage IOL = -2mA (Memory pads excepted) High level output voltage IOH = 2mA (SSTL pads excepted) Low level output voltage IOL = -2mA (SSTL pads only) High level output voltage IOH = 2mA (SSTL pads only) VC18 power supply current (crystal freq. = 12.288 MHz, all 3 P24 running) VC18 power supply current (crystal freq. = 12.288 MHz, all P24 stopped, warm start power-down active) VC18 deep power down supply current (using power switch) VC33 power supply current (crystal freq.= 12.288 MHz) VC25 power supply current (crystal freq.= 12.288 MHz, RS = 25, RT = 50) Built-in pull-up / pull-down resistor Min -0.3 2 VREF+0.31 -0.3 1.235 VC33-0.4 VC25-0.4 10 Typ 46 4 1 1 75 Max 0.8 3.6 VREF-0.31 0.605 VC18+0.3 0.4 0.4 10 56 Unit V V V V V V V V V V mA mA A mA mA kOhm Table 8-4. Symbol VIL VIH VIL VIH VIL VIH VOL VOH VOL VOH IC18 IC18 IC18 IC33 IC25 PU/PD 18 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 9. Peripherals and Timings 9.1 Slave 8-bit Parallel Interface Pins used: D7-D0 (I/O), CS (input), A0 (input), WR (input), RD (input), IRQ (output) This interface is typically used to connect the chip to a host processor. 9.1.1 Timings Figure 9-1. A0 t A V CS CS t CS LRDL RD t RDLDV D0-D7 t DRH t P RD t RDHCSH Host Interface Read Cycle Figure 9-2. A0 Host Interface Write Cycle t AVCS CS t CSLWRL WR t DWS D0-D7 t DWH t PWR t WRHCSH Table 9-1. Symbol tAVCS tCSLRDL tRDHCSH tPRD tRDLDV tDRH tCSLWRL tWRHCSH Timing Parameters Parameter Address valid to chip select low Chip select low to RD low RD high to CS high RD pulse width Data out valid from RD Data out hold from RD Chip select low to WR low WR high to CS high Min 0 5 5 50 1.7 5 5 Typ Max 20 10 Unit ns ns ns ns ns ns ns ns 19 6237A-DRMSD-29-May-06 Table 9-1. Symbol tPWR tDWS tDWH Timing Parameters Parameter WR pulse width Write data setup time Write data hold time Min 50 10 0.9 Typ Max Unit ns ns ns 9.1.2 IO Status Register TE RF X X X X X X Status register is read when A0 = 1, RD = 0, CS = 0 * TE: Transmit empty If 0, data from ATSAM3703 to host is pending and IRQ is high. Reading the data at A0 = 0 sets TE to 1 and clear IRQ. * RF: Receiver full If 0, then ATSAM3703 is ready to accept DATA from host. Note: If status bit RF is not checked by host, write cycle time should not be lower than 3 s. 9.2 SmartMedia and Other Peripheral Interfaces This is a master 8-bit parallel interface, allowing connection to SmartMedia or other peripherals such as LCD screens. Pins used: * I/O7 - I/O0 (I/O) * SMPD (input) * SMCE, SMALE, SMCLE, SMRE, SMWE (outputs) All these pins are fully under firmware control, therefore timing compatibility is ensured by firmware only. 9.3 Serial Slave Synchronous Interface The SAM3303 can be controlled by an external host processor through the unidirectional serial interface. However, no firmware can be downloaded at power-up through this interface. Therefore an external ROM/Flash/EEPROM is required. Pins used: * SCLK, SYNC, SDIN (input) * INT (output) Data is shifted MSB first. The IC samples an incoming SDIN bit on the rising edge of SCLK, therefore the host should change SDIN on the negative SCLK edge. SYNC allows initial synchronization. The rising edge of SYNC, which should occur with SCLK low, indicates that SDIN holds MSB data on the next rising SCLK. The data is stored internally into a 256 bytes FIFO. When the FIFO count is below 64, the INT output goes low. This allows the host processor to send data in burst mode. 20 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 The maximum SCLK frequency is fCK (fCK is the crystal frequency). The minimum time between two bytes is 64 fCK periods. The contents of the SDIN data are defined by the firmware. Figure 9-3. SCLK Typical Interface Timing for Serial Slave SYNC SDIN MSB 9.4 9.4.1 External DDR SDRAM and SDRAM Memories Overview The ATSAM3703 supports the DDR SDRAM components compatible with JEDEC standard (JESD79D). Following memories can be connected to the ATSAM3703: * DDR SDRAM, 4 bits wide * SDRAM, 4 bits wide DDR SDRAM and SDRAM cannot be connected at the same time. The type of connection is SSTL_2 for DDR SDRAM and LVTTL for SDRAM. DDR SDRAM and SDRAM use time multiplexed addressing with a ROW/COL scheme (banks WBA0 to WBA1 and address lines WA0 to WA11). 9.4.2 9.4.2.1 Double Data Rate SDRAM Memory Size The data bus is 4 bits wide. Due to the 12-bit address bus, the maximum accessible address space is 128 Mbits (32M x 4). Larger components are supported, but only a part of the address space is used. DDR SDRAM Memory Size Bank Address 2 bits 2 bits 2 bits 2 bits 2 bits Row Address 12 bits 12 bits 13 bits 13 bits 14 bits Column Address 10 bits 11 bits 11 bits Only 12-bit rows are used (only 128 Mbits are accessible). 12 bits 12 bits Only 12-bit rows are used (only 128 Mbits are accessible). Self-refresh might not be supported (depending on to tXSNR value; see below) Remark Table 9-2. DDR Size 64 Mbits (16 M x 4) 128 Mbits (32 M x 4) 256 Mbits (64 M x 4) 512 Mbits (128 M x 4) 1 Gbits (256 M x4) 21 6237A-DRMSD-29-May-06 9.4.2.2 Pinning Table 9-3. DDR SDRAM Pinning DDR Pin A13, A12 A11..A0 BA1, BA0 DQ3..DQ0 DQS DM Description Unused address bits (for larger device). Must be tied to zero. Address Bank address Data Data strobe Data mask. Must be tied to zero. Differential clock Clock enable Chip select. Must be tied to zero. ATSAM3703 Pin WA11..WA0 WBA1, WBA0 WD3..WD0 WDQS WCK, WCK WCKE WCAS WRAS WWE VREF CK, CK CKE CS CAS RAS WE VREF Command SSTL_2 reference voltage. Must be connected to 1.25 V. 9.4.2.3 Timing General Parameters The DDR SDRAM is used with parameters defined in Table 9-4. Table 9-4. Symbol tCK CL Mode Register Burst type Operating mode DLL Extended mode register Output drive strength normal sequential normal enabled DDR SDRAM General Parameters Parameter Clock cycle time CAS Latency Burst length Value 10 ns 2 cycles 4 data 22 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 Command Sequencing The ATSAM3703 supports DDR200 and faster DDR devices, and thus the DDR device must support parameters defined in Table 9-5. Table 9-5. Symbol tMRD tRAS tRC tRFC tRCD tRP tRRD tWR tWTR tXSNR tXSRD tREFI Supported Parameters Parameter MODE REGISTER SET command cycle time ACTIVE to PRECHARGE command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH to ACTIVE/AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period ACTIVE bank a to ACTIVE bank b command WRITE recovery time Internal WRITE to READ command delay Exit self refresh to non-READ command Exit self refresh to READ command Average periodic REFRESH interval Value min 20 ns min 50 ns max 70 us min 70 ns min 120 ns min 20 ns min 20 ns min 20 ns min 20 ns min 10 ns min 80 ns min 2 us 7.8 us ATSAM3703 to DDR Table 9-6. Symbol tIH tIS tDSS tDSH tDS tDH Parameters Parameter Address and control hold time Address and control setup time DQS falling edge to CK setup time DQS falling edge hold time from CK DQ and DM setup time DQ and DM hold time Value min 3.6 ns min 3.2 ns min 4.3 ns min 4.3 ns min 1.7 ns min 0.8 ns DDR to ATSAM3703 The data from DDR to ATSAM3703 must meet timing requirements defined in Table 9-7. These parameters are applicable at input of ATSAM3703, and must include effects of DDR device and effects of board layout. 23 6237A-DRMSD-29-May-06 Table 9-7. Symbol tDQSQ tDQSCK Timing Requirements Parameter Skew between WDQS, WD3, WD2, WD1 and WD0 Delay from WCK, WCK to WDQS (excluding CAS latency) Value max 1.6 ns max 5 ns 9.4.3 9.4.3.1 Single Data Rate SDRAM Memory Size The data bus is 4 bits wide. Due to the 12-bit address bus, the maximum accessible address space is 128 Mbits (32M x 4). Larger components are supported, but only a part of the address space is used. SDR SDRAM Memory Size Bank Address 2 bits 2 bits 2 bits 2 bits Row Address 12 bits 12 bits 13 bits 13 bits Column Address 10 bits 11 bits 11 bits 12 bits Only 12-bit rows are used (only 128 Mbits are accessible) Remark Table 9-8. DDR Size 64 Mbits (16M x 4) 128 Mbits (32M x 4) 256 Mbits (64M x 4) 512 Mbits (128M x 4) 9.4.3.2 Pinning Table 9-9. SDR Pinning SDR Pin A13, A12 A11..A0 BA1, BA0 DQ3..DQ0 DM Description Unused address bits (for larger device). Must be tied to zero. Address Bank address Data Not used. Must be left unconnected. Data mask. Must be tied to zero. Clock Not used. Must be left unconnected. Clock enable Chip select. Must be tied to zero. ATSAM3703 Pin WA11..WA0 WBA1, WBA0 WD3..WD0 WDQS WCK WCK WCKE WCAS WRAS WWE VREF CK CKE CS CAS RAS WE - Command Must be connected to VC25/2. 24 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 9.4.3.3 Timing General Parameters The SDR is used with parameters as in Table 9-10. Table 9-10. Symbol tCK CL SDR General Parameters Parameter Clock cycle time CAS Latency Burst length Mode Register Burst type Operating mode Output drive strength Value (50 MHz) 20 ns 2 cycles 4 data sequential normal normal Value (100 MHz) 10 ns 2 cycles 4 data sequential normal normal Command Sequencing The SDRAM device must support following parameters. Table 9-11. Symbol tMRD tRAS tRC tRFC tRCD tRP tRRD tWR tXSNR tXSRD tREFI Supported Parameters Parameter MODE REGISTER SET command cycle time ACTIVE to PRECHARGE command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH to ACTIVE/AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period ACTIVE bank a to ACTIVE bank b command WRITE recovery time Exit self refresh to non-READ command Exit self refresh to READ command Average periodic REFRESH interval Value (50 MHz) min 40 ns min 60 ns max 70 us min 80 ns min 80 ns min 20 ns min 20 ns min 20 ns min 20 ns min 80 ns min 4 us 7.8 us Value (100 MHz) min 20 ns min 50 ns max 70 us min 70 ns min 70 ns min 20 ns min 20 ns min 20 ns min 20 ns min 80 ns min 2 us 7.8 us 25 6237A-DRMSD-29-May-06 ATSAM3703 to SDRAM The outputs of ATSAM3703 meet constraints as in Table 9-12. Table 9-12. Symbol tIH tIS tDS tDH ATSAM9703 Output Constraints Parameter Address and control hold time Address and control setup time DQ and DM setup time DQ and DM hold time Value(50 MHz) min 8.8 ns min 8.3 ns min 14.3 ns min 3.8 ns Value(100 MHz) min 3.8 ns min 3.3 ns min 6.8 ns min 1.4 ns SDR to ATSAM3703 The data from SDR to ATSAM3703 must meet following timing requirements. These parameters are applicable at input of ATSAM3703, and must include effects of SDR device and effects of board layout. Table 9-13. Parameter DQ setup time DQ hold time Timing Requirements Value min 2.0 ns min 1.8 ns 9.4.4 Address Mapping For information, the mapping in Table 9-14 is applied from the internal async bus address AAD[22:0] to the SDRAM address. Table 9-14. Address Mapping Value at RAS time AAD0 AAD1 AAD10 AAD11 AAD12 AAD13 AAD14 AAD15 AAD16 AAD17 AAD18 AAD19 AAD20 AAD21 Value at CAS time AAD0 AAD1 0 (see note) 0 (see note) AAD2 AAD3 AAD4 AAD5 AAD6 AAD7 AAD8 AAD9 Auto-Precharge AAD22 ATSAM3703 Address Bus WBA0 WBA1 WA0 WA1 WA2 WA3 WA4 WA5 WA6 WA7 WA8 WA9 WA10 WA11 Note: WA[1:0] = 00 at CAS time means that for each read or write operation at a specified address, four nibbles are read or write in the burst sequential order (0,1, 2, 3). Other sequential orders are not allowed. 26 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 9.5 Digital Audio Pins used: * CLBD, WSBD (outputs) * DABD3 - 0 (outputs) * DAAD3 - 0 (inputs) And optionally * CLAD3 - 0, WSAD3 - 0 (inputs) The ATSAM3703 allows for 8 digital audio output channels and 8 digital audio input channels. All audio channels are normally synchronized on single clocks CLBD, WSBD which are derived from the IC crystal oscillator. However, as a firmware option, the DAAD3 - 0 inputs can be synchronized with incoming CLAD3 - 0 and WSAD3 - 0 signals. In this case, the incoming sampling frequencies must be lower or equal to the chip sampling frequency. The digital audio timing follows the I2S standard, with up to 24 bits per sample. Figure 9-4. Digital Audio Timing tCW WSBD tCW tCLBD CLBD tSOD DABD3 - 0 DAAD3 - 0 tSOD Table 9-15. Symbol tCW tSOD tCLBD Digital Audio Timing Parameters Parameter CLBD rising to WSBD change DABD valid prior/after CLBD rising CLBD cycle time Min tC - 10 tC - 10 Typ 2*tc Max Unit ns ns ns tC is related to tCK, the crystal period at X1, as shown in Table 9-16. Table 9-16. Sample Frequency Typical Sample Frequency 96 kHz 64 kHz 48 kHz 32 kHz tC tCK 2 * tCK 2 * tCK 4 * tCK CLBD/WSBD Freq Ratio 64 48 64 48 Sample Frequency WSBD 1/(tCK * 128) 1/(tCK * 192) 1/(tCK * 256) 1/(tCK * 384) The choice of sample frequency is done by the firmware. 27 6237A-DRMSD-29-May-06 9.5.1 Digital Audio Frame Format ATSAM3703 can generate I2S or MSB left justified digital audio format. Master Clock CLBD can be 128 x Fs, 256 x Fs, 512 x Fs, 192 x Fs, 384 x FS or 768 x Fs. Format and clock ratio are selected by firmware. I2S Digital Audio Frame Format,128 x Fs, 256 x Fs and 512 x Fs Modes Figure 9-5. WSBD CLBD DABD3 - 0 DAAD3 - 0 MSB LSB (16 bits) LSB (24 bits) MSB Figure 9-6. WSBD I2S Digital Audio Frame Format,192 x Fs, 384 x Fs and 768 x Fs Modes CLBD DABD3 - 0 DAAD3 - 0 MSB LSB (16 bits) LSB (24 bits) MSB Figure 9-7. WSBD CLBD DABD3 - 0 DAAD3 - 0 MSB Left Justified Digital Audio Frame Format,128 x Fs, 256 x Fs and 512 x Fs Modes MSB LSB (16 bits) LSB (24 bits) MSB Figure 9-8. WSBD MSB Left Justified Digital Audio Frame Format,192 x Fs, 384 x Fs and 768 x Fs Modes CLBD DABD3 - 0 DAAD3 - 0 MSB LSB (16 bits) LSB (24 bits) MSB 28 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 9.6 Serial MIDI_IN and MIDI_OUT The serial MIDI IN and OUT signals are asynchronous signals following the MIDI transmission standard: * Baud rate: 31.25 kHz * Format: start bit(0), 8 data bits, stop bit(1) 29 6237A-DRMSD-29-May-06 10. Reset and Power Down During power-up, the RESET input should be held low until the crystal oscillator and PLL are stabilized, which takes max. 10ms. After the low to high transition of RESET, the following occurs: * All P24s enter an idle state. * P16 program execution starts in built-in ROM. The power-up sequence is as follows: * STIN is sensed. If HIGH, then the built-in debugger is started. * Addresses 0 &1 from internal EEPROM are checked. If "DR" is read, then control is transferred to address 400H from internal EEPROM. * SMC is sensed. If LOW, then the built-in loader waits for SmartMedia presence detect (SMPD). When detected, the firmware is downloaded from SmartMedia reserved sector 1 and started. * Firmware download from an host processor is assumed. (Download in 8K x 24 internal RAM) 1. The byte 0ACh is written to the host, this rises IRQ. The host can recognize that the chip is ready to accept program download. Higher speed transfer can be reach by polling the parallel interface status (CS=0, A0=1, RD=0). 2. The host sends the firmware size (in words) on two bytes (low byte first). 3. The host sends the ATSAM3703 firmware. The firmware should begin with string "DR". 4. The byte 0ACh is written to the host, this rises IRQ. The host can recognize that the chip has accepted the firmware. 5. ATSAM3703 starts the firmware. If PDWN is asserted low, then the crystal oscillator and PLL are stopped. If the power switch is used, then the chip enters a deep power down sleep mode, as power is removed from the core. To exit power down, PDWN has to be asserted high, then RESET applied. Other power reduction features allowing warm restart are controlled by firmware: * P24s can be individually stopped. * The clock frequency can be internally divided by 256. 30 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 11. Recommended Board Layout Like all HCMOS high integration ICs, the following rules for board layout are mandatory for reliable operations. 11.1 GND, VC33, VC25, VC18 Distribution, Decoupling All GND, VC33, VC25, VC18 pins should be connected. A GND plane is strongly recommended. The board GND, VC33, VC25 and VC18 distribution should be in grid form. Recommended VC18 decoupling is 0.1F at each VC18 pin of the IC with an additional 10FT decoupling close to the crystal. Minimum recommended VC25 decoupling is 0.1F at pin 22, 42 and 55. VC33 requires a single 0.1F decoupling. 11.2 Crystal The paths between the crystal, the crystal compensation capacitors and the IC should be short and shielded. The ground return from the compensation capacitors filter should be the GND plane from the IC. 11.3 Buses Parallel layout from D0-D7 and WA0-WA11/WDQ0-WDQ3 should be avoided. The D0-D7 bus is an asynchronous type bus. Even on short distances, it can induce pulses on WA0WA11/WDQ0-WDQ3 which can corrupt address and/or data on these buses. A ground plane should be implemented below the D0-D7 bus, which connects both to the host and to the IC GND. A ground plane should be implemented below the WA0-WA11/WDQ0-WDQ3 bus, which connects both to the SDRAM or DDR SDRAM grounds and to the IC. 11.4 DDR SDRAM and SDRAM The routing of all signals must be as symmetric as possible. This applies particularly to WDQS, WDQ3, WDQ2, WDQ1 and WDQ0 signals. The routing of all signals should be kept as short as possible. VREF must be equal to VC25/2, generated with a resistive divider. Both resistors must have the same value (1% precision). Suggested range is 50 - 150 Ohm. Proper decoupling at each VREF pin (controller, VREF source and RAM device) is recommended. The SSTL2 signals (DDR) must use a parallel termination (47 Ohm, for example). This termination must be connected to VTT (VC25/2). This VTT is generated from a special component (able to source or to sink current) using VREF as reference. This termination must be placed just after DDR device. 11.5 Analog Section A specific AGND ground plane should be provided, which connects by a single trace to the GND ground. No digital signals should cross the AGND plane. Refer to the Codec vendor recommended layout for correct implementation of the analog section. 31 6237A-DRMSD-29-May-06 12. Recommended Crystal Compensation Figure 12-1. Recommended Crystal Compensation 64 X1 63 X1 X2 C2 22 pF C1 22 pF GND GND 32 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 13. Product Development and Debugging Atmel provides an integrated product development and debugging tool SamVS. SamVS runs under Windows(R) (98, ME, 2000, XP). Within the environment, it is possible to: * Edit * Assemble * Debug on real target (In Circuit Emulation) * Program internal EEPROM, SmartMedia on target. Two dedicated IC pins, STIN and STOUT, permit running the firmware directly into the target using standard PC COM port communication at 57.6 Kbauds. Thus time to market is optimized by testing directly on the final prototype. A library of frequently used functions is available: * Reverb * Chorus * Delay * Compressor * Pitch shifter * Distortion * Flanger * Phaser * Vocoder * Feedback canceller * MP3 decode * 31 band equalizer * Parametric equalizer Atmel engineers are available to study customer specific applications. 33 6237A-DRMSD-29-May-06 14. Ordering Information Table 14-1. Ordering Information Package LQFP80 Package Type Green Ordering Code ATSAM3703 34 ATSAM3703 6237A-DRMSD-29-May-06 ATSAM3703 15. Revision History Table 15-1. Revision History Comments First issue Change Request Ref. Document Ref. 6237A 35 6237A-DRMSD-29-May-06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) Atmel Corporation 2006. All rights reserved. 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